1. Field of the Invention
The present invention relates to a picture coding apparatus and more specifically, to a picture coding apparatus comprising a dedicated LSI for picture coding.
2. Description of the Related Art
A conventional picture coding apparatus comprises plural specialized LSIs for picture coding. A CPU is mounted on each of the LSIs and a frame memory is coupled with each of the LSIs.
For example, a picture coding comprising three kinds of specialized LSIs for picture coding is described in 17.1.1 "A Chip Set Architecture for Programmable Real-Time MPEG Video Encoder" (on pages 393-396) of preliminary paper of IEEE COSTOM INTEGRATED CIRCUITS CONFERENCE hold in May 1995. FIG. 2 of the title shows that three memory chips are necessary for the encoder. FIG. 4 and 6 of the title show that two of the three LSIs have controlling processors. Moreover, In 17.1.2 "A Single Chip, 5 GOPS, Macroblock-Level Pixel Processor for MPEG" Real-Time Encoding" (on pages 397-400) of the preliminary paper, the details of one of the three LSIs, a pixel processor, is described. FIG. 7 of the title shows that RISC unit occupies about 20 percent of the chip area.
For another example, a CODEC which comprises two kinds of specialized LSIs for picture coding are described with reference to FIGS. 8 and 9 in "MPEG2 VIDEO CODEC USING IMAGE COMPRESSION DSP" on pages 466-472 of IEEE Transactions on Consumer Electronics, Vol. 40, No. 3 published in August 1994. It is apparent that two LSIs has their own memory chips.
Another example of the similar system is described on pages 2-7 of an issue the February 1996 of "Denshi Gijutsu (Electronics Technology)" published by Nikkan Kogyo newspaper office in Japan. FIG. 7 on page 6 shows that each of two kinds of LSIs necessitates its own memory. It is described that one chip (VDSP) of the two kinds of LSI adapts a programmable architecture.
For further example, on page 98 of proceedings of lecture of Hot Chips VII, a video encoder comprising two kinds of specialized LSIs for picture coding is described. FIG. 4.1-08 shows that the encoder comprises two kinds of chips for picture coding: ENC-M and ENC-C. FIG. 4.1-12 shows that controlling processor occupies one-fourth area of ENC-C chip.
ENC-M chip is described in "A Real-time Motion Estimation and Compensation LSI with Wide-Search Range for MPEG2 Video Encoding" on pages 242-243 and 453 of a digest of technical papers of IEEE International Solid-State Circuits Conference. FIG. 6 on page 453 of the title shows that controlling processor (RISC) occupies one-fourth area of the LSI.
For still further example, a similar picture coding apparatus is described in C-562, on page 178, of a preliminary papers of meeting of the Institute of Electronics, Information and Communication Engineers hold in March 1996 in Japan. The figures on the page shows that two kinds of memory chips are required in the apparatus.
For more further example, a picture coding apparatus comprising three kinds of specialized LSIs is described on page 105 of proceedings of Hot Chips VII. FIG. 4.2-06 of the title shows the structure. Although the internal structure is not described apparently, it is specified that the system requires three kinds of memory chips as well as the number of LSI chips.
One problem of the aforementioned picture coding apparatuses is that plural kinds of specialized LSIs are required, the size of the LSIs are large, and the cost for manufacturing the apparatus using them becomes high eventually. The increase of the area by 20 to 30 percent when using a CPU in a specialized LSI for picture coding results in the increase of cost. The necessity of a CPU in a picture coding LSI is caused by including programmable portion for controlling itself. Although the programmable portion is not required if the picture coding LSI is designed based on beforehand and sufficient consideration on the specification, too much programmable portion accompanying increase of chip area is introduced to make the chip more flexible than required for tuning up the picture coding apparatus.
Second problem of the aforementioned picture coding apparatus is that the number of components increases and eventually the cost and power consumption of the apparatus increase. In addition to plural picture coding LSI chips, plural memory chips belonging to each of LSI chips are required. This is caused because it is impossible to integrate every picture coding functions containing too much programmable portions in one chip using LSI process nowadays.